1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to an apparatus and method for controlling a bank of a semiconductor memory apparatus.
2. Related Art
In general, as shown in FIG. 1, the apparatus for controlling the bank of a semiconductor memory apparatus includes first to fourth bank areas 10 to 40, each of which has a plurality of banks (banks 0 to 3), and a peripheral circuit unit 50 that outputs a bank selection signal casp8<0:3> and a first address gay<2:9>. Further, FIG. 2 is a layout diagram of the configuration of FIG. 1. Here, the first address gay<2:9> is a column address for selecting a predetermined column of the bank.
Since the first to fourth bank areas 10 to 40 have the same structure, only the internal structure of the first bank area 10 is shown in FIG. 1. The structure is described below.
The first bank area 10 includes the plurality of banks (banks 0 to 3), and column controllers 11 to 14 that control the plurality of banks (banks 0 to 3), respectively. Here, each of the column controllers 11 to 14 generates a second address, which has a timing margin through a logic circuit and a delay element, by using each bit of the bank selection signal casp8<0:3> and the first address gay<2:9>.
Further, each of the column controllers 11 to 14 controls input and output of data at each of the banks (banks 0 to 3) by using the second address according to a clock timing.
However, the apparatus for controlling the bank of a semiconductor memory apparatus according to the related art has the following problems.
First, since the column controller controls the bank according to a clock timing, the column controller ensures a timing margin for performing the control operation according to a clock by delaying an address. However, variation in clock time affects the delay time. Further, as the clock time is reduced, it is difficult to ensure an exact delay time, and thus an error may occur in generating an address. In the case of a high-frequency system, the clock time is further reduced, and an error is more likely to occur in generating an address. Therefore, it is difficult to apply the apparatus for controlling bank of a semiconductor memory apparatus according to the related art to a high-frequency system.
Second, a layout area is increased because each of the column controllers has a delay logic for generating an address, and signal lines for supplying a bank selection signal and an address to each of the column controllers are formed, as shown in FIG. 2.
Third, unnecessary power is consumed because internal logic circuits of the corresponding column controller operate regardless of whether bank selection is made or not.